System for driving columns of a liquid crystal display

ABSTRACT

A system for driving columns of a liquid crystal display includes logic circuitry operating in a supply path between a first and a second supply voltage in which the first supply voltage is higher than the second supply voltage. The logic circuitry is capable of generating first logic signals and second logic signals whose value is equal to the first or second supply voltage. The system includes two level shifters coupled to the logic circuitry and operating in a supply path between a third supply voltage greater than the first supply voltage and the second supply voltage; the level shifters are capable of raising the value of the second logic signals. The system also includes a first and a second pair of transistors having different supply paths and having an output terminal in common; the first and the second pair of transistors are coupled to the level shifters to determine the drive signal of a column. The system includes turnoff circuitry operating in a supply path between the third and the second supply voltage and coupled to the two level shifters. The turnoff circuitry is capable of keeping one of the two pairs of transistors in a turnoff state in the period of time of a frame when the other of the two pairs of transistors is operative.

FIELD OF THE INVENTION

The present invention relates to a system for driving columns of aliquid crystal display.

BACKGROUND OF THE INVENTION

Liquid crystal displays (LCD) are used today in an ever-increasingnumber of products such as cellular telephones, portable computers, etc.The displays, which can be in black and white, or in a grey or colorscale, are usually made up of a matrix of electrodes in rows andcolumns. When driven by an appropriate voltage signal, a change in theoptic behavior occurs at the crossing points of the rows and columns(“pixels”).

The image that is visualized on the display is obtained throughdifferent possible methods for driving the rows and the columns.

One method that is often used for driving an LCD is known as ImprovedAlt & Pleshko (IA&P) and requires a single row electrode to be excitedfor an elementary period of time by a single selection pulse and thesimultaneous excitation of the column electrodes. Voltage values arethen applied to the column electrodes suitable for causing all thepixels that belong to that single row to be turned on or turned off. Fora successive period of elementary time there is an excitation of anotherrow electrode and so on until the scanning of the last row electrode iscompleted; therefore if the row electrodes are a number N and T is theperiod of elementary time, the time needed for scanning all the rowswill be given by NT which is also called a “frame”.

The optic transmission characteristics of the liquid crystal vary withthe amplitude of the voltage applied to the relative pixel, but theapplication of direct voltage is damaging to the liquid crystal as itpermanently changes and degrades the physical properties of thematerial. For this reason, the voltage signals used to drive the singlepixels of an LCD are alternating voltage in relation to a common valueof direct voltage that is not necessarily ground potential. In thismanner, the driving of a pixel of the display comes about through twowaveforms of equal amplitude but with opposite polarity in relation to acommon voltage, that follow each other periodically. Therefore thedriving voltage applied to a given pixel during its period T within aframe is applied with opposite polarity during the respective period Tof the successive frame.

Nevertheless, all these voltage transitions involve significant powerthat has to be managed by the drive circuits. Therefore, one of theprimary purposes in planning the LCD row and column driving devices isto reduce the power consumption to minimize both the power delivered bythe power supplies of said devices, and the power dissipated by them.

One part of a driving device of LCD rows and columns, more precisely thePhilips PCF8548 device, is shown in FIG. 1.

The LOW_FRAME signal is a logic signal that equals zero in the evenframes, and equals one in the uneven frames. WHITE_PIX is a logic signalthat equals zero when the pixel is on, and equals one when the pixel isoff. Starting from these two signals are generated, through a circuit 1,the control signals that drive two PMOS transistors T9, T10 and two NMOStransistors T7, T8.

In particular, the gate terminals of transistors T8, T9 and T10 aredriven through 3 identical circuit cells C1, shown in FIG. 2. Said cellsare level-shifters that is, buffers that convert the logic signal levelsfrom a low voltage to a high voltage, in particular, from the supplyvoltage VDD to a driving voltage VLCD generated by a device (not shownin FIG. 2) comprising a booster regulator through the connection of acertain number of stages of a charge pump.

Each cell C1 comprises two NMOS transistors M22 and M23 driven bysignals A and NA, the output signal of the logic circuitry 1 and thenegated signal A. The source terminals of transistors M22 and M23 arecoupled to the voltage VSS and the drain terminals are respectivelycoupled to the drain terminals of two PMOS transistors M20 and M21 onthe source terminal of which the voltage VLCD is present; in additionthe drain terminals of transistors M22 and M23 are coupled to the gateterminals of transistors M21 and M20. The outputs Q drive the gate oftransistors T10, T9 and T8.

The gate terminal of transistor T7 is driven directly by a logic lowvoltage signal.

The source terminal of the transistor T9 is connected to a voltagereference VA, while the drain terminal is coupled to the drain terminalof transistor T10, whose source terminal is coupled to the voltage VLCD.The source terminal of transistor T8 is coupled to a voltage referenceVB, while the drain terminal is coupled to the drain terminal oftransistor T7, whose source terminal is coupled to the voltage VSS. Thedrain terminals of the pairs of transistor T7-T8 and T9-T10 are incommon and supply the output signal OUT.

The voltages VA and VB are different levels of intermediate voltagesbetween the voltages VLCD and VSS that are generated inside the drivedevice of an LCD. The relation between these levels and VLCD is chosenon the basis of the dimension of the matrix of the display according tothe criteria that is shown and described below.

In particular, according to the technique of Improved Alt & Pleshko, todrive the liquid crystal display adequately, four different voltagelevels intermediate between VLCD and VSS are generated inside thedevice. The relation between these and VLCD is set on the basis of thenumber of rows m of the display according to the relations:VLCD,[(n+3)/(n+4)]*VLCD,[(n+2)/(n+4)]*VLCD,[2/(n+4)]*VLCD,[1/(n+4)]*VLCD,VSS)with n given by {square root}m−3.

If, for example, m=81=>n=6 in the case of a display with 81 rows thevoltage levels will be:VLCD (9/10)*VLCD (8/10)*VLCD (2/10)*VLCD (1/10)*VLCD VSS.

With reference to the drive circuit of FIG. 1, in the case of a drive ofcolumns, the voltage references VA and VB are equal respectively to(8/10)*VLCD and (2/10)*VLCD. The drive is provided, for example, in thefollowing manner: in a frame transistors T9 and T10 are turned onalternately, while transistors T7 and T8 are off; in this case theoutput signal OUT, suitable for driving a column, varies between VLCDand VA according to whether the corresponding pixel on the matrix ofrows and columns given at the crossing point of the column and the rowis on or not. In the successive frame transistors T7 and T8 are turnedon alternately while transistors T9 and T10 are off and therefore theoutput signal varies between VSS and VB according to whether the pixelat the crossing point of the corresponding column and row is on or not.The waveforms of the output signal OUT in the case of driving twocolumns COL0 and COL1 for a frame n and for the successive frame n+1 areshown in FIG. 3. FIG. 4 shows the image as it appears on the display.

What is desired is a system for driving columns of a liquid crystaldisplay that has lower current consumption in comparison to known priorart devices.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a system fordriving columns of a liquid crystal display includes logic circuitryoperating in a supply path between a first and a second supply voltagewith first said supply voltage higher than said second supply voltage,said logic circuitry being capable of generating starting from firstlogic signals in input second logic signals in output whose value isequal to said first or second supply voltage, elevator devices coupledto said logic circuitry and operating in a supply path between a thirdsupply voltage greater than said first supply voltage and said secondsupply voltage, said elevator devices being capable of raising the valueof said second logic signals, a first and a second pair of transistorshaving different supply paths and having an output terminal in common,said first and second pairs of transistors being associated to saidelevator devices and to said logic circuitry so as to determine thedrive signal of a column, wherein there are two elevator devices andeach of them is coupled to one of said pairs of transistors, andincludes turnoff circuitry coupled to said two elevator devices, saidcircuitry being capable of keeping one of the two pairs of transistorsin the turnoff state in the period of time of a frame when the other ofsaid two couples of transistors is operative.

BRIEF DESCRIPTION OF THE DRAWINGS

The characteristics and the advantages of the present invention willappear evident from the following detailed description of an embodimentthereof illustrated as non-limiting example in the enclosed drawings, inwhich:

FIG. 1 is a circuitry diagram of a driving device of columns of an LCDaccording to the known art;

FIG. 2 is a more detailed circuitry diagram of a part of the circuit ofFIG. 1;

FIG. 3 shows waveforms of the output voltage signal of the circuit ofFIG. 1 in the case of driving two columns;

FIG. 4 shows an image formed on the display of an LCD;

FIG. 5 is a circuitry diagram of a system for driving the columns of anLCD according to an embodiment of the invention;

FIG. 6 is a more detailed circuitry diagram of the device of FIG. 5; and

FIG. 7 shows the temporal waveforms LOW_FRAME, WHITE_PIX, CN, CN_N, CP,CP_N and OUT concerning the circuit of FIG. 6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 5 shows a circuit diagram of a system for driving columns of an LCDaccording to an embodiment of the present invention. Said devicecomprises a low voltage logic circuit 10 operating between a supplyvoltage VDD and a supply voltage VSS, two level-shifters 11 and 12operating between a supply voltage VLCD supplied by a device comprisinga booster regulator through the connection of a certain number of stagesof a charge pump (not shown in FIG. 5) and the voltage VSS, a pair ofPMOS transistors T11, T12 and a pair of NMOS transistors T13, T14 havingdifferent supply paths. The principle on which the invention is based isthat in a frame transistors PMOS T11, T12 or both transistors NMOS T13,T14 are never both on. This permits the elimination of a level-shifterin relation to the drive device of FIG. 1, as every level-shiftercomprises in addition to the output signal its negated signal, but it isnecessary to add circuitry to keep the MOS transistors not involved inthe commutation during the abovementioned frame off; a decrease of thecurrent used in the drive device of the columns derives from this.Therefore the device of FIG. 5 also comprises turnoff circuitry 15capable of generating two signals TR_STATE1 and TR_STATE2 suitable forturning off, alternately through level-shifters 11 and 12, PMOStransistors T 11, T12 or NMOS transistors T13, T14 not involved in thecommutations with the succession of the frame.

The signal LOW_FRAME is a logic signal that equals zero in the evenframes, and equalling one in the uneven frames. WHITE_PIX is a logicsignal that equals zero when the pixel has is on, and equalling one whenthe pixel is off. Starting from these two signals, through circuit 10,the logic signals CP, CP_N, CN, CN N, suitable for driving thelevel-shifters 11 and 12 are generated, which in turn drive PMOStransistors T11, T12 and NMOS transistors T13, T14.

Circuit 10 ensures that if the logic signal LOW_FRAME is at the onelogic level, the signals CP and CP_N are placed at the zero logic leveland the signals CN and CN_N commutate following the commutation of thesignal WHITE_PIX; more precisely, the signal CN is in phase with thesignal WHITE_PIX while the signal CN_N is the signal CN negated.

Given that the logic signals CP and CP_N are at the zero logic level,the level-shifter 11 that is driven by said signals must be inactive sothat PMOS transistors T11 and T12 are off. In this case, the TR_STATE1signal generated by circuitry 15 keeps level-shifter 11 inactive. NMOStransistors T13, T14 are driven by level-shifter 12, which is operatingand the output OUT of the column drive device varies between VSS and VB.

Again, circuit 10 ensures that if the logic signal LOW_FRAME is at thezero logic level, the signals CN and CN_N are placed at the one logiclevel and the signals CP and CP_N commutate following the commutationsof the signal WHITE_PIX; more precisely the signal CP is in phase withthe signal WHITE_PIX while the signal CP_N is the signal CP negated.

Given that the logic signals CN and CN_N are at the one logic level,level-shifter 12 that is driven by said signals must be inactive so thatNMOS transistors T13 and T14 are off. In this case, the TR_STATE2 signalgenerated by circuitry 15 keeps level-shifter 12 inactive. PMOStransistors T11, T12 are driven by level-shifter 11 operating and theoutput OUT of the column drive device varies between VLCD and VA.

FIG. 7 shows the temporal diagrams of the signals LOW_FRAME, WHITE_PIX,CN, CN_N, CP, CP_N, OUT that derive from simulations relating to twosuccessive frames, that is an even frame and an uneven frame.

FIG. 6 shows the components of the column drive device of FIG. 5 more indetail.

The low voltage logic circuitry 10 comprises several inverters as wellas NAND and NOR gates which, starting from the signals WHITE_PIX andLOW_FRAME in input to the circuitry 10 generate the logic signals CP,CP_N, CN, CN_N, suitable for driving level-shifters 11 and 12 and havinga voltage value equal to the voltage VDD or to the voltage VSS as shownin FIG. 6.

Device 11 comprises two NMOS transistors M8 and M9 driven by the signalsCP and CP_N, whose source terminals are coupled to the voltage VSS andwhose drain terminals are coupled respectively to the drain terminals oftwo PMOS transistors M4 and M5 on the source terminal of which thevoltage VLCD is present. The gate terminals of transistors M4 and M5 arecoupled to the drain terminals of transistors M9 and M8.

The same drain terminals of transistors M8 and M9 are coupled to thegate terminals of transistors M2 and M1 on the source terminals of whichthe voltage VLCD is present, and at the drain terminals of transistorsM3 and M6 on the source terminals of which the voltage VLCD is present.Transistors M1, M2, M3, M6 belong to turnoff circuitry 15 that alsocomprises a transistor M7 having its source terminal coupled to thevoltage VSS, the drain terminal in common with the gate terminal oftransistors M3 and M6 and with the drain terminals of transistors M1 andM2; the signal LOW_FRAME is present on the gate terminal.

Device 12 comprises two NMOS transistors M14 and M15 driven by thesignals CN and CN_N whose source terminals are coupled to the voltageVSS and whose drain terminals are coupled respectively to the drainterminals of two PMOS transistors M12 and M13 the gate terminals ofwhich are coupled to the drain terminals of transistors M15 and M14. Thesource terminals of transistors M12 and M13 are coupled to the drainterminals of two transistors M10 and M11 having the gate terminals incommon and the voltage VLCD is present on the source terminals. The gateterminal of transistors M10 and M11 is connected to the gate terminal oftransistor M6.

The pair of PMOS transistors T11 and T12 has a supply path between thevoltages VLCD and VA while NMOS transistors T13 and T14 has a supplypath between the voltages VB and VSS. The gate terminals of transistorsT11 and T12 are coupled to the drain terminals of transistors M8 and M9of device 11, while the gate terminals of transistors T13 and T14 arecoupled with the drain terminals of transistors M15 and M14 of device12. The common output terminal of transistors T11 and T12 is coupled tothe common output terminal of transistors T13 and T14 and represents theoutput terminal OUT of the drive device of the present invention.

Circuit 10 ensures that, as can be seen in FIG. 6, if the logic signalLOW_FRAME is at the one logic level, the signals CP and CP_N are placedat the zero logic level and the signals CN and CN_N commutate followingthe commutations of the signal WHITE_PIX; more precisely, the signal CNis in phase with the signal WHITE_PIX while the signal CN_N is thesignal CN negated.

With the logic signals CP and CP_N at the zero logic level,level-shifter 11 is inactive and PMOS transistors T11 and T12 are off.In fact, transistor M7 is on and causes transistors M3 and M6 to turn onas it brings the voltage on their gate terminals at VSS; in this manner,the voltage on the gate terminals of the transistors T11 and T12 isbrought to a voltage that is substantially the same as VLCD bytransistors M3 and M6. The turning on of transistor M7 causestransistors M10 and M11 to turn on, bringing the voltage on the sourceterminals of transistors M12 and M13 substantially the same as VLCD. Inthis case, the TR_STATE1 signal generated by circuitry 15 is high andkeeps level-shifter 11 inactive; the TR_STATE2 signal is low and permitsdevice 12 to turn on. The NMOS transistors T13, T14 are driven bylevel-shifter 12 operating and the output OUT of the column drive devicevaries between VSS and VB.

Again, circuit 10 ensures that if the logic signal LOW_FRAME is at thezero logic level, the signals CN and CN_N are placed at the one logiclevel and the signals CP and CP_N commutate following the commutationsof the signal WHITE_PIX; more precisely, the signal CP is in phase withthe signal WHITE_PIX while the signal CP_N is the signal CP negated.

With the logic signals CN and CN_N at the one logic level, level-shifter12 is inactive and NMOS transistors T13 and T14 are off. In fact,transistor M7 is off and the turning on of one of transistors M8 or M9causes one of transistors M2 or M1 to turn on as it brings the voltageon their gate terminals to VSS; in this manner, the voltage on one ofthe gate terminals of transistors T11 and T12 is brought to a voltagewhich is substantially equal to VSS. The turning on of one oftransistors M1 or M2 causes transistors M3 and M6 to turn off andtransistors M10 and M11 that inhibit the turning on of device 12 and oftransistors T13 and T14 to turn off. In this case, the TR_STATE2 signalgenerated by circuitry 15 is high and keeps level-shifter 12 inactive;the TR_STATE1 signal is low and permits device 11 to turn on. The PMOStransistors T11, T12 are driven by level-shifter 11 operating and theoutput OUT of the column drive device varies between VLCD and VA.

While there have been described above the principles of the presentinvention in conjunction with a specific circuit and timingimplementation it is to be clearly understood that the foregoingdescription is made only by way of example and not as a limitation tothe scope of the invention. Particularly, it is recognized that theteachings of the foregoing disclosure will suggest other modificationsto those persons skilled in the relevant art. Such modifications mayinvolve other features which are already known per se and which may beused instead of or in addition to features already described herein.Although claims have been formulated in this application to particularcombinations of features, it should be understood that the scope of thedisclosure herein also includes any novel feature or any novelcombination of features disclosed either explicitly or implicitly or anygeneralization or modification thereof which would be apparent topersons skilled in the relevant art, whether or not such relates to thesame invention as presently claimed in any claim and whether or not itmitigates any or all of the same technical problems as confronted by thepresent invention. The applicants hereby reserve the right to formulatenew claims to such features and/or combinations of such features duringthe prosecution of the present application or of any further applicationderived therefrom.

1. A system for driving columns of a liquid crystal display comprising:logic circuitry operating in a supply path between a first and a secondsupply voltage with said first supply voltage higher than said secondsupply voltage, said logic circuitry being capable of generating firstlogic signals and second logic signals whose value is equal to saidfirst or second; elevator devices coupled to said logic circuitry andoperating in a supply path between a third supply voltage greater thansaid first supply voltage and said second supply voltage, said elevatordevices being capable of raising the value of said second logic signals;a first and a second pair of transistors having different supply pathsand having an output terminal in common, said first and second pair oftransistors being associated with said elevator devices and said logiccircuitry to determine the drive signal of a column, wherein saidelevator devices are coupled to one of said pairs of transistors; andturnoff circuitry coupled to said elevator devices, said turnoffcircuitry being capable of keeping one of said two pairs of transistorsin the turnoff state in the period of time of a frame when the other ofsaid two pairs of transistors is operative.
 2. The system according toclaim 1, wherein said turnoff circuitry operates in a supply pathbetween said third and said second supply voltage.
 3. The systemaccording to claim 1, wherein each of said elevator devices separatelydrives the transistors of one of said pairs, of transistors.
 4. Thesystem according to claim 3, wherein said turnoff circuitry one of saidfirst logic signals in changes value in response to an even frame or anuneven frame.
 5. The system according to claim 4, wherein said turnoffcircuitry sends two signals complementary with each other respectivelyto said elevator devices according to the state of one of said firstlogic signals to inhibit the turning on of one of the elevator devices.6. The system according to claim 5, wherein said pairs of transistorscomprise pairs of MOS transistors.
 7. They system according to claim 6,wherein said pairs of MOS transistors comprise a pair of PMOStransistors and a pair of NMOS transistors, and said elevator deviceseach comprise a first and a second NMOS transistor driven by two of saidsecond logic signals complementary between each other and a first and asecond PMOS transistor having terminals that can be driven coupledrespectively with the drain terminal of said second and first NMOStransistors, the drain terminals coupled respectively with the drainterminals of said first and second NMOS transistors, and the sourceterminals coupled to said third supply voltage.
 8. The system accordingto claim 7, wherein said turnoff circuitry comprises a first transistorhaving a gate terminal driven by said one of first logic signals andhaving a first non-driven terminal coupled to said second supply voltageand a second non-driven terminal coupled to non-driven terminals of twoadditional transistors having a first non-driven terminal coupledrespectively with the drain terminals of said first and second NMOStransistor of one of said elevator devices and a second non-driventerminal coupled to said third supply voltage, the non-driven terminalof said two additional transistors being coupled to the non-driventerminal in common with two more additional transistors having firstnon-driven terminals respectively coupled to the source terminals ofsaid first and second PMOS transistor of one of said elevator devicesand the other non-driven terminal coupled to the third supply voltage,said turnoff circuitry comprising two more additional transistors havingnon-driven terminals respectively coupled to the drain terminals of saidfirst and second NMOS transistor of one of said elevator devices, firstnon-driven terminals coupled to said additional non-driven terminal ofsaid first transistor and second non-driven terminal coupled to saidthird supply voltage.